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high speed, triple differential receiver with comparators ad8143 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features high speed 160 mhz large signal bandwidth 1000 v/s slew rate @ g = 1, v o = 2 v p-p high cmrr: 65 db @ 10 mhz high differential input impedance: 5 m input common-mode range: 10.5 v (12 v supplies) user-adjustable gain wide power supply range: +5 v to 12 v fast settling: 8 ns to 1% disable feature low offset: 3.4 mv on 5 v supply 2 on-chip comparators small packaging: 32-lead, 5 mm 5 mm lfcsp applications rgb video receivers kvm (keyboard-video-mouse) utp (unshielded twisted pair) receivers pin configuration ref_g gnd in+_g fb_g ref_r in?_g gnd fb_r out_b gnd out_r out_g compb_in+ v s+ gnd compb_in? in?_b gnd fb_b in+_b dis/pd ref_b gnd v s? in+_r gnd compa_in+ in?_r compa_out compa_in? gnd compb_out ad8143 a b 05538-001 32 31 30 29 28 27 26 25 9 10111213141516 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 figure 1. general description the ad8143 is a triple, low cost, differential-to- single-ended receiver specifically designed for receiving red-green-blue (rgb) signals over twisted pair cable. it can also be used for receiving any type of analog signal or high speed data transmission. two auxiliary comparators are provided to receive digital or sync signals. the ad8143 can be used in conjunction with the ad8133 and ad8134 triple, differential drivers to provide a complete low cost solution for rgb over category-5 utp cable applications, including kvm. the excellent common-mode rejection (65 db @ 10 mhz) of the ad8143 allows for the use of low cost unshielded twisted pair cables in noisy environments. the ad8143 has a wide power supply range from single +5 v supply to 12 v, which allows for a wide common-mode range. the wide common-mode input range of the ad8143 maintains signal integrity in systems where the ground potential is a few volts different between the drive and receive ends without the use of isolation transformers. the ad8143 is stable at a gain of 1. closed-loop gain is easily set using external resistors. the ad8143 is available in a 5 mm 5 mm, 32-lead lfcsp and is rated to work over the extended industrial temperature range of ?40c to +85c.
ad8143 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configuration ............................................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 17 applications ..................................................................................... 18 overview ..................................................................................... 18 basic closed-loop gain configurations ................................ 18 terminating the input ................................................................ 19 input clamping ........................................................................... 19 printed circuit board layout considerations ....................... 20 driving a capacitive load ......................................................... 22 power-down ............................................................................... 22 comparators ............................................................................... 22 sync pulse extraction using comparators ............................. 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 10/05revision 0: initial version
ad8143 rev. 0 | page 3 of 24 specifications v s = 12 v, t a = 25c, ref = 0 v, r l = 150 , c l = 2 pf, g = 1, t min to t max = ?40c to +85c, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out = 0.2 v p-p 260 mhz v out = 2 v p-p 160 mhz bandwidth for 0.1db flatness v out = 0.2 v p-p 45 mhz slew rate v out = 2 v p-p, r l = 1 k 1000 v/s settling time v out = 2 v p-p, 1% 8 ns v out = 2 v p-p, 0.1% 31 ns output overdrive recovery 50 ns noise/distortion second harmonic v out = 2 v p-p, 1 mhz ?70 dbc third harmonic v out = 2 v p-p, 1 mhz ?80 dbc crosstalk v out = 1 v p-p, 10 mhz ?70 db input voltage noise (rti) f 10 khz 14 nv/hz differential gain error ntsc, 200 ire, r l 150 0.03 % differential phase error ntsc, 200 ire, r l 150 0.06 degrees input characteristics common-mode rejection dc, v cm = ?3.5 v to +3.5 v 86 90 db v cm = 1 v p-p, f = 10 mhz 65 db v cm = 1 v p-p, f = 100 mhz 28 db common-mode voltage range v +in ? v ?in = 0 v 10.5 v differential operating range 2.5 v resistance differential 5 m common-mode 3 m capacitance differential 2 pf common-mode 3 pf dc performance open-loop gain v out = 1 v 70 db closed-loop gain error dc 0.25 % input offset voltage ?4.3 +4.3 mv t min to t max 15 v/c input bias current (+in, ?in) ?3.0 +3.0 a input bias current (ref, fb) ?4.6 +3.7 a input bias current drift t min to t max (+in, ?in) 16 na/c input offset current (+in, ?in, ref, fb) ?2.55 +1.45 a input offset current drift t min to t max 3 na/c output performance voltage swing r load = 1 k ?10.80 +10.82 v output current 40 ma short circuit current short to gnd, source/sink 107/147 ma comparator performance v oh 3.135 3.3 v v ol 0.2 0.255 v hysteresis width 41 mv input bias current input driven low 3.5 a propagation delay, t plh r l = 10 k 20 ns propagation delay, t phl r l = 10 k 15 ns output rise time 25% to 75%, r l = 10 k 15 ns output fall time 25% to 75%, r l = 10 k 11 ns
ad8143 rev. 0 | page 4 of 24 parameter conditions min typ max unit power-down performance power-down v ih v s+ ? 1.5 v power-down v il v s+ ? 2.5 v power-down i ih pd = v cc 1.0 a power-down i il pd = gnd 800 a power-down assert time 0.5 s power supply operating range 4.5 24 v quiescent current, positive supply 44.0 57.5 ma quiescent current, negative supply 37.0 51.0 ma psrr, positive supply dc ?75 ?71 db psrr, negative supply dc ?82 ?81 db
ad8143 rev. 0 | page 5 of 24 v s = 5 v, t a = 25c, ref = 0 v, r l = 150 , c l = 2 pf, g = 1, t min to t max = ?40c to +85c, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out = 0.2 v p-p 230 mhz v out = 2 v p-p 130 mhz bandwidth for 0.1db flatness v out = 0.2 v p-p 45 mhz slew rate v out = 2 v p-p, r l = 1 k 1000 v/s settling time v out = 2 v p-p, 1% 10 ns v out = 2 v p-p, 0.1% 23 ns output overdrive recovery 50 ns noise/distortion second harmonic v out = 1 v p-p, 1 mhz ?68 dbc third harmonic v out = 1 v p-p, 1 mhz ?82 dbc crosstalk v out = 1 v p-p, 10 mhz ?70 db input voltage noise (rti) f 10 khz 14 nv/hz differential gain error ntsc, 200 ire, r l 150 0.3 % differential phase error ntsc, 200 ire, r l 150 0.6 degrees input characteristics common-mode rejection dc, v cm = ?3.5 v to +3.5 v 84 90 db v cm = 1 v p-p, f = 10 mhz 65 db v cm = 1 v p-p, f = 100 mhz 28 db common-mode voltage range v +in ? v ?in = 0 v 3.8 v differential operating range 2.5 v resistance differential 5 m common-mode 3 m capacitance differential 2 pf common-mode 3 pf dc performance open-loop gain v out = 1 v 70 db closed-loop gain error dc 0.25 % input offset voltage ?3.7 +3.7 mv t min to t max 15 v/c input bias current (+in, ?in) ?3.0 +2.7 a input bias current (ref, fb) ?4.3 +3.0 a input bias current drift t min to t max (+in, ?in, ref, fb) 16 na/c input offset current (+in, ?in, ref, fb) ?2.9 1.9 a input offset current drift t min to t max 3 na/c output performance voltage swing r load = 150 ?3.53 +3.53 v output current 40 ma short circuit current short to gnd, source/sink 107/147 ma comparator performance v oh r l = 10 k 3.02 3.14 v v ol r l = 10 k 0.19 0.25 v hysteresis width 32 mv input bias current input driven low 3.5 a propagation delay, t plh 20 ns propagation delay, t phl 15 ns output rise time 10% to 90% 15 ns output fall time 10% to 90% 11 ns
ad8143 rev. 0 | page 6 of 24 parameter conditions min typ max unit power-down performance power-down v ih v s+ ? 1.5 v power-down v il v s+ ? 2.5 v power-down i ih pd = v cc 1 a power-down i il pd = gnd 230 a power-down assert time 0.5 s power supply operating range 4.5 24 v quiescent current, positive supply 39.0 49.5 ma quiescent current, negative supply 34.5 43.5 ma psrr, positive supply dc ?80 ?74 db psrr, negative supply dc ?80 ?75 db
ad8143 rev. 0 | page 7 of 24 v s = 5 v, t a = 25c, ref = +2.5 v, r l = 150 , c l = 2 pf, g = 1, t min to t max = ?40c to +85c, unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out = 0.2 v p-p 220 mhz v out = 2 v p-p 125 mhz bandwidth for 0.1db flatness v out = 0.2 v p-p 45 mhz slew rate v out = 2 v p-p, r l = 1 k 1000 v/s settling time v out = 2 v p-p, 1% 10 ns v out = 2 v p-p, 0.1% 23 ns output overdrive recovery 50 ns noise crosstalk v out = 1 v p-p, 10 mhz ?70 db input voltage noise (rti) f 10 khz 14 nv/hz input characteristics common-mode rejection dc, v cm = ?3.5 v to +3.5 v 76 90 db v cm = 1 v p-p, f = 10 mhz 65 db v cm = 1 v p-p, f = 100 mhz 32 db common-mode voltage range v +in ? v ?in = 0 v 1.3 to 3.7 v differential operating range 2.5 v resistance differential 5 m common-mode 3 m capacitance differential 2 pf common-mode 3 pf dc performance open-loop gain v out = 1 v 70 db closed-loop gain error dc, measured at g = 11 0.25 % input offset voltage ?3.4 +3.4 mv t min to t max 15 v/c input bias current (+in, ?in) ?3 +2.7 a input bias current (ref, fb) ?4.5 +3 a input bias current drift t min to t max (+in, ?in, ref, fb) 16 na/c input offset current (+in, ?in, ref, fb) ?2.3 +1.3 a input offset current drift t min to t max 3 na/c output performance voltage swing r load = 150 0.88 3.58 v output current 40 ma short circuit current short to gnd 150 ma comparator performance v oh r l = 10 k 3.02 v v ol r l = 10 k 0.25 v hysteresis width 32 mv input bias current input driven low 3.5 a propagation delay, t plh 20 ns propagation delay, t phl 15 ns output rise time 10% to 90% 15 ns output fall time 10% to 90% 11 ns power-down performance power-down v ih v s+ ? 1.5 v power-down v il v s+ ? 2.5 v power-down i ih pd = v cc 1 a power-down i il pd = gnd 230 a power-down assert time 0.5 s
ad8143 rev. 0 | page 8 of 24 parameter conditions min typ max unit power supply operating range 4.5 24 v quiescent current, positive supply 31.5 38.8 ma psrr, positive supply dc ?86 ?76 db
ad8143 rev. 0 | page 9 of 24 absolute maximum ratings table 4. parameter rating supply voltage 24 v power dissipation see figure 2 storage temperature range C65c to +125c operating temperature range C40c to +85c lead temperature range (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the pcb surface which is thermally connected to a copper plane. table 5. thermal resistance package type ja jc unit 5 mm 5 mm, 32-lead lfcsp 45 7 c/w maximum power dissipation the maximum safe power dissipation in the ad8143 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8143. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. for each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. the power dissipated due to all of the loads is equal to the sum of the power dissipation due to each individual load. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb surface which is thermally connected to a copper plane to achieve the specified ja . figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 32-lead lfcsp (45c/w) on a jedec standard 4-layer board with the underside paddle soldered to a pad which is thermally connected to a pcb plane. extra thermal relief is required for operation at high supply voltages. see the applications section for details. ja values are approximations. 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?40?200 20406080 ambient temperature (c) maximum power dissipation (w) 05538-056 figure 2. maximum power dissipation vs. temperature for a 4-layer board esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8143 rev. 0 | page 10 of 24 pin configuration and fu nction descriptions ref_g gnd in+_g fb_g ref_r in?_g gnd fb_r out_b gnd out_r out_g compb_in+ v s+ gnd compb_in? in?_b gnd fb_b in+_b dis/pd ref_b gnd v s? in+_r gnd compa_in+ in?_r compa_out compa_in? gnd compb_out ad8143 top view (not to scale) a b 05538-050 32 31 30 29 28 27 26 25 9 10111213141516 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 figure 3. 32-lead lfcsp pin configuration note exposed pad on underside of device must be connected to ground. table 6. 32-lead lfcsp pin function descriptions pin no. mnemonic description 1, 8, 9,16, 17, 24, 25, 32 gnd signal ground and thermal plane connection (see the applications section) 2 ref_g reference input, green channel 3 fb_g feedback input, green channel 4 in+_g noninverting input, green channel 5 in?_g inverting input, green channel 6 ref_r reference input, red channel 7 fb_r feedback input, red channel 10 in+_r noninverting input, red channel 11 in?_r inverting input, red channel 12 compa_in+ positive input, comparator a 13 compa_in? negative input, comparator a 14 compa_out output, comparator a 15 compb_out output, comparator b 18 compb_in? negative input, comparator b 19 compb_in+ positive input, comparator b 20 v s+ positive power supply 21 out_r output, red channel 22 out_g output, green channel 23 out_b output, blue channel 26 v s? negative power supply 27 dis/pd disable/power down 28 ref_b reference input, blue channel 29 fb_b feedback input, blue channel 30 in+_b noninverting input, blue channel 31 in?_b inverting input, blue channel exposed underside pad gnd signal ground and thermal plane connection (see the applications section)
ad8143 rev. 0 | page 11 of 24 typical performance characteristics unless otherwise noted, g = 1, r l = 150 , c l = 2 pf, v s = 5 v, t a = 25c. refer to the circuit in figure 38 . 3 ?7 1 10 100 05538-002 frequency (mhz) gain (db) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v out = 0.2v p-p v s =5 v s = 12 v s = +5 figure 4. small signal frequency response at various power supplies, g = 1 9 ?1 1 10 100 05538-003 frequency (mhz) gain (db) 8 7 6 5 4 4 2 1 0 v out = 0.2v p-p v s =5 v s = 12 v s = +5 figure 5. small signal frequency response at various power supplies, g = 2 3 ?7 11 01 0 0 05538-004 frequency (mhz) gain (db) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v out =0.2vp-p r l =1k r l = 150 figure 6. small signal frequency response at various loads 3 ?7 1 10 100 05538-005 frequency (mhz) gain (db) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v s =5 v s = 12 v s = +5 v out = 2v p-p figure 7. large signal frequency response at various power supplies, g = 1 9 ?1 1 10 100 05538-006 frequency (mhz) gain (db) 8 7 6 5 4 3 2 1 0 v s =5 v s = 12 v s = +5 v out = 2v p-p figure 8. large signal frequency response at various power supplies, g = 2 3 1 10 100 05538-007 frequency (mhz) gain (db) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 r l = 1k r l = 150 v out = 2v p-p figure 9. large signal frequency response at various loads
ad8143 rev. 0 | page 12 of 24 5 ?5 1 1000 05538-013 frequency (mhz) gain (db) 10 100 4 3 2 1 0 ?1 ?2 ?3 ?4 r l = 1k v out = 0.2v p-p g = 1, c l = 2pf g = 1, c l = 10pf, r snub = 40 g = 2, c l = 2pf g = 2, c l = 10pf, r snub = 40 figure 10. small signal frequency response at various gains and 10 pf capacitive load buffe red by 40 resistor 3 ?7 1 10 100 05538-009 frequency (mhz) gain (db) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v out = 0.2v p-p g = 1 g = 2 figure 11. small signal frequency response at various gains 0.5 ?0.5 1 100 05538-010 frequency (mhz) gain (db) 10 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 r l = 150 , v out = 0.2v p-p r l = 150 , v out = 2v p-p r l = 1k , v out = 0.2v p-p r l = 1k , v out = 2v p-p figure 12. 0.1 db flatness for various loads and output amplitudes 5 ?5 1 1000 05538-014 frequency (mhz) gain (db) 10 100 4 3 2 1 0 ?1 ?2 ?3 ?4 g = 1, c l = 2pf g = 1, c l = 10pf, r snub = 40 g = 2, c l = 2pf g = 2, c l = 10pf, r snub = 40 r l = 1k v out = 2v p-p figure 13. large signal frequency response at various gains and 10 pf capacitive load buffe red by 40 resistor 3 ?7 1 10 100 05538-012 frequency (mhz) gain (db) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 g = 1 g = 2 v out = 2v p-p figure 14. large signal frequency response at various gains 80 ?10 0.001 1000 05538-016 frequency (mhz) open loop-gain (db) 0.01 0.1 1 10 100 70 50 60 40 30 20 10 0 0 ?180 open loop-phase (degrees) ?20 ?60 ?40 ?80 ?100 ?120 ?140 ?160 magnitude phase figure 15. open-loop gain and phase responses
ad8143 rev. 0 | page 13 of 24 100 0 0.1 1000 05538-020 frequency (mhz) common-mode rejection (db) 1 10 100 90 80 70 60 50 40 30 20 10 5v 12v +5v figure 16. common-mode rejection ratio vs. frequency at various supplies 200 ?200 0 100 05538-015 time (ns) voltage (mv) 150 100 50 0 ?50 ?100 ?150 10 20 30 40 50 60 70 80 90 v out = 0.2v p-p g = 1, r l = 150 g = 1, r l = 1k g = 2, r l = 150 g = 2, r l = 1k figure 17. small signal transient response at various gains and loads 200 ?200 0 100 05538-017 time (ns) output voltage (mv) 150 100 50 0 ?50 ?100 ?150 10 20 30 40 50 60 70 80 90 r l = 1k v out = 0.2v p-p g = 2, c l = 2pf g = 2, c l = 10pf, r snub = 40 g = 1, c l = 2pf g = 1, c l = 10pf, r snub = 40 figure 18. small signal transient response at various gains and 10 pf capacitive load buffe red by 40 resistor 100 10 0.00001 10 05538-021 frequency (mhz) input voltage noise (nv/ hz) 0.0001 0.001 0.01 0.1 1 v s = 12v figure 19. input referred voltage noise vs. frequency 1.5 ?1.5 0 100 05538-018 time (ns) voltage (v) 1.0 0.5 ?0.5 0 ?1.0 10 20 30 40 50 60 70 80 90 v out = 2v p-p g = 1, r l = 150 g = 1, r l = 1k g = 2, r l = 150 g = 2, r l = 1k figure 20. large signal transient response at various gains and loads 1.5 ?1.5 0 100 05538-019 time (ns) output voltage (db) 1.0 0.5 0 ?0.5 ?1.0 10 20 30 40 50 60 70 80 90 g = 2, c l = 2pf g = 2, c l = 10pf, r snub = 40 g = 1, c l = 2pf g=1,c l = 10pf, r snub =40 r l = 1k v out = 2v p-p figure 21. large signal transient response at various gains and 10 pf capacitive load buffe red by 40 resistor
ad8143 rev. 0 | page 14 of 24 1.25 ?1.25 0 100 05538-027 time (ns) voltage (v) 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 0.5 ?0.5 error (%) 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 10 20 30 40 50 60 70 80 90 input output error figure 22. settling time (0.1%) at various loads ? 50 ?80 0.1 100 05538-047 frequency (mhz) distortion (dbc) 11 0 ?55 ?60 ?65 ?70 ?75 v s = 5v v s = 12v figure 23. second harmonic distortion vs. frequency and power supplies, v o = 2 v p-p, g = 2 ?50 ?75 0.1 100 05538-048 frequency (mhz) distortion (dbc) 11 0 ?55 ?60 ?65 ?70 v s = 5v v s = 12v figure 24. second harmonic distortion vs. frequency and power supplies, v o = 2 v p-p 1400 0 0 4.5 05538-023 output voltage (v p-p) slew rate (v/ s) 1200 1000 800 600 400 200 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 +sr, r l = 150 ?sr, r l = 150 +sr, r l = 1k ?sr, r l = 1k figure 25. slew rate vs. input voltage swing at various loads ?30 ?100 0.1 100 05538-055 frequency (mhz) distortion (dbc) 11 0 ?40 ?50 ?60 ?70 ?80 ?90 vs = 12v vs = 5v figure 26. third harmonic distortion vs. frequency and power supplies, v o = 2 v p-p, g = 2 ? 30 ?90 0.1 100 05538-049 frequency (mhz) distortion (dbc) 11 0 ?40 ?50 ?60 ?70 ?80 v s =5v v s = 12v figure 27. third harmonic distortion vs. frequency and power supplies, v o = 2 v p-p
ad8143 rev. 0 | page 15 of 24 54 38 ?5 5 05538-022 differential input voltage (v) supply current (ma) 52 50 48 46 44 42 40 ?4?3?2?101234 v s = 12v r l = i s ? i s + figure 28. power supply current vs. differential input voltage at 12 v supplies 60 10 ?50 100 05538-031 temperature ( c) supply current (ma) 55 50 45 40 35 30 25 20 15 ?40?30?20?100 102030405060708090 r l = i s +, v s = 12v i s ?, v s = 12v i s +, v s = 5v i s ?, v s = 5v figure 29. power supply current vs. temperature 0 ?100 0.01 1000 05538-046 frequency (mhz) psrr (db) 0.1 1 10 100 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 v s = 5v v s = 12v v s = +5v figure 30. positive power supply rejection ratio vs. frequency 4 ?4 ?3 ?2 ?1 ?5 5 05538-026 differential input voltage (v) output voltage (v) ?4?3?2?1 01234 3 2 1 0 figure 31. differential input operating range 50 25 5 12 05538-024 supply voltage ( v s ) supply current (ma) 45 40 35 30 67891011 i s ? i s + r l = figure 32. power supply curren t vs. power supply voltage 0 ?100 0.01 1000 05538-045 frequency (mhz) psrr (db) 0.1 1 10 100 ?90 ?80 ?70 ?60 ?50 ?40 ?20 ?30 ?10 v s = 5v v s = 12v figure 33. negative power supply rejection ratio vs. frequency
ad8143 rev. 0 | page 16 of 24 15 ?15 0 1000 05538-025 output load ( ) output voltage (v) 10 5 0 ?5 ?10 100 200 300 400 500 600 700 800 900 +v sat _5v ?v sat _5v ?v sat _12v +v sat _12v g = +2 (r f = r g = 499 ) and v s =5v g = +5 (r f = 8.06k r g = 2k ) and v s = 12v figure 34. output saturation voltage vs. output load 6 ?6 0 1000 05538-029 time (ns) voltage (v) 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 100 200 300 400 500 600 700 800 900 2 v in output g = 2 figure 35. output overdrive recovery 4.0 0 ?25 25 05538-032 v in (mv) v out (v) ?20 ?10 ?5 0 5 10 15 20 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ?15 v s = 12v v s = 5v figure 36. comparator hysteresis
ad8143 rev. 0 | page 17 of 24 theory of operation the ad8143 amplifiers use an architecture called active feedback, which differs from that of conventional op amps. the most obvious differentiating feature is the presence of two separate pairs of differential inputs compared to a conventional op amps single pair. typically, for the active-feedback architecture, one of these input pairs is driven by a differential input signal, while the other is used for the feedback. this active stage in the feedback path is where the term active feedback is derived. the active feedback architecture offers several advantages over a conventional op amp in several types of applications. among these are excellent common-mode rejection, wide input common- mode range, and a pair of inputs that are high impedance and completely balanced in a typical application. in addition, while an external feedback network establishes the gain response as in a conventional op amp, its separate path makes it entirely independent of the signal input. this eliminates any interaction between the feedback and input circuits, which traditionally causes problems with cmrr in conventional differential-input op amp circuits. another advantage of active feedback is the ability to change the polarity of the gain merely by switching the differential inputs. a high input impedance inverting amplifier can therefore be made. besides high input impedance, a unity-gain inverter with the ad8143 has noise gain of unity, producing lower output noise and higher bandwidth than op amps that have noise gain equal to 2 for a unity-gain inverter. the two differential input stages of the ad8143 are each transconductance stages that are well-matched. these stages convert the respective differential input voltages to internal currents. the currents are then summed and converted to a voltage, which is buffered to drive the output. the compensation capacitor is included in the summing circuit. when the feedback path is closed around the part, the output drives the feedback input to that voltage which causes the internal currents to sum to zero. this occurs when the two differential inputs are equal and opposite; that is, their algebraic sum is zero. in a closed-loop application, a conventional op amp has its differential input voltage driven to near zero under non- transient conditions. the ad8143 generally has differential input voltages at each of its input pairs, even under equilibrium conditions. as a practical consideration, it is necessary to internally limit the differential input voltage with a clamp circuit. thus, the input dynamic ranges are limited to about 2.5 v for the ad8143 (see specifications section for more detail). for this and other reasons, it is not recommended to reverse the input and feedback stages of the ad8143, even though some apparently normal functionality may be observed under some conditions.
ad8143 rev. 0 | page 18 of 24 applications overview the ad8143 contains three independent active-feedback amplifiers that can be effectively applied as differential line receivers for red-green-blue (rgb) signals or component video, such as ypbpr, signals transmitted over unshielded-twisted-pair (utp) cable. the ad8143 also contains two general-purpose comparators with hysteresis that can be used to receive digital signals or to extract video synchronization pulses from received common-mode signals that contain encoded synchronization signals. an internal linear voltage regulator derives power for the comparators from the positive supply; therefore, the ad8143 must always have a minimum positive supply voltage of 4.5 v. the ad8143 includes a power-down feature that can be asserted to reduce the supply current when a particular device is not in use. basic closed-loop gain configurations as described in the theory of operation section, placing a resistive feedback network between an amplifier output and its respective feedback amplifier input creates a stable negative feedback amplifier. it is important to note that the closed-loop gain of the amplifier used in the signal path is defined as the amplifiers single-ended output voltage divided by its differential input voltage. therefore, each amplifier in the ad8143 provides differential-to-single-ended gain. additionally, the amplifier used for feedback has two high impedance inputsthe fb input, where the negative feedback is applied, and the ref input, which can be used as an independent single-ended input to apply a dc offset to the output signal. some basic gain configurations implemented with an ad8143 amplifier are shown in figure 37 through figure 39 . + ? + ? +5v ?5v ref v ref fb r g r f 0.01 f 0.01 f v in v out 05538-038 figure 37. basic gain circuit: v out = (v in + v ref )(1 + r f /r g ) the gain equation for the circuit in figure 37 is v out = ( v in + v ref )(1 + r f / r g ) (1) in this configuration, the voltage applied to the ref pin appears at the output with a gain of 1 + r f /r g . to achie ve u nit y gain f rom v ref to v out in this configuration, divide v ref by the same factor used in the feedback loop; the same r f and r g values can be used. figure 38 illustrates this approach. + ? + ? +5v ?5v ref v ref fb r g r g r f r f 0.01 f 0.01 f v in v out 05538-039 figure 38. basic gain circuit: v out = v in (1 + r f /r g ) + v ref the gain equation for the circuit in figure 38 is v out = v in (1 + r f / r g ) + v ref (2) another configuration that provides the same gain equation as equation 2 is shown in figure 39 . in this configuration, it is important to keep the source resistance of v ref much smaller than r g to avoid gain errors. + ? + ? +5v ?5v ref fb r g r f 0.01 f 0.01 f v in v out 05538-040 v ref figure 39. basic gain circuit: v out = v in (1 + r f /r g ) + v ref for stability reasons, the inductance of the trace connected to the ref pin must be kept to less than 10 nh. the typical inductance of 50 traces on the outer layers of the fr-4 boards is 7 nh/in, and on the inner layers, it is typically 9 nh/in. vias must be accounted for as well. the inductance of a typical via in a 0.062-inch board is on the order of 1.5 nh. if longer traces are required, a 200 resistor should be placed in series with the trace to reduce the q-factor of the inductance.
ad8143 rev. 0 | page 19 of 24 in many dual-supply applications, v ref can be directly connected to ground right at the device. terminating the input one of the key benefits of the active-feedback architecture is the separation that exists between the differential input signal and the feedback network. because of this separation, the differential input maintains its high cmrr and provides high differential and common-mode input impedances, making line termination a simple task. most applications that use the ad8143 involve transmitting broadband video signals over 100 utp cable and use dc-coupled terminations. the two most common types of dc-coupled terminations are differential and common-mode. differential termination of 100 utp is implemented by simply connecting a 100 resistor across the amplifier input, as shown in figure 40 . + ? +5v ?5v ref fb r g r f 0.01 f 0.01 f + ? v in v out 05538-041 100 utp 100 figure 40. differential-mode termination some applications require common-mode terminations for common-mode currents generated at the transmitter. in these cases, the 100 termination resistor is split into two 50 resistors. the required common-mode termination voltage is applied at the tap between the two resistors. in many of these applications, the common-mode tap is connected to ground (v term (cm) = 0). this scheme is illustrated in figure 41 . + ? +5v ?5v ref fb r g r f 0.01 f 0.01 f + ? v in v out v term (cm) 05538-042 100 utp 50 50 figure 41. common-mode termination input clamping the differential input that is assigned to receive the input signal includes clamping diodes that limit the differential input swing to approximately 5.5 v p-p at 25c. because of this, the input and feedback stages should never be interchanged. figure 31 illustrates the clamping action at the signal input stage. the supply current drawn by the ad8143 has a strong dependence on input signal magnitude because the input transconductance stages operate with differential input signals that can be up to a few volts peak-to-peak. this behavior is distinctly different from that of traditional op-amps, where the differential input signal is driven to essentially 0 v by negative feedback. figure 28 illustrates the supply current dependence on input voltage. for most applications, including receiving rgb video signals, the input signal magnitudes encountered are well within the safe operating limits of the ad8143 over its full power supply and operating temperature ranges. in some extreme applications where large differential and/or common-mode voltages can be encountered, external clamping may be necessary. another application where external common-mode clamping is sometimes required is when an unpowered ad8143 receives a signal from an active driver. in this case, external diodes are required when the current drawn by the internal esd diodes cannot be kept to less than 5 ma. when using 12 v supplies, the differential input signal must be kept to less than 4 v p-p. in applications that use 12 v supplies where the input signals are expected to reach or exceed 4 v p-p, external differential clamping at a maximum of 4 v p-p is required. figure 42 shows a general approach to external differential- mode clamping. positive clamp negative clam p r s r t v in v out r s ? + ? + 05538-051 figure 42. differential-mode clamping the positive and negative clamps are nonlinear devices that exhibit very low impedance when the voltage across them reaches a critical threshold (clamping voltage), thereby limiting the voltage across the ad8143 input. the positive clamp has a positive threshold, and the negative clamp has a negative threshold.
ad8143 rev. 0 | page 20 of 24 a diode is a simple example of such a clamp. schottky diodes generally have lower clamping voltages than typical signal diodes. the clamping voltage should be larger than the largest expected signal amplitude, with enough margin to ensure that the received signal passes without being distorted. a simple way to implement a clamp is to use a number of diodes in series. the resultant clamping voltage is then the sum of the clamping voltages of individual diodes. a 1n4448 diode has a forward voltage of approximately 0.70 v to 0.75 v at typical current levels that are seen when it is being used as a clamp, and 2 pf maximum capacitance at 0 v bias. (the capacitance of a diode decreases as its reverse bias voltage is increased.) the series connection of two 1n4448 diodes, therefore, has a clamping voltage of 1.4 v to 1.5 v. figure 43 shows how to limit the differential input voltage applied to an ad8143 amplifier to 1.4 v to 1.5 v (2.8 v p-p to 3.0 v p-p). note that the resulting capacitance of the two series diodes is half that of one diode. different numbers of series diodes can be used to obtain different clamping voltages. r t is the differential termination resistor and the series resistances, r s , limit the current into the diodes. the series resistors should be highly matched in value to preserve high frequency cmrr. positive clamp negative clamp r s r t v in r s ? + 05538-052 v out ? + figure 43. using two 1n4448 diodes in series as a clamp there are many other nonlinear devices that can be used as clamps. the best choice for a particular application depends upon the desired clamping voltage, response time, parasitic capacitance, and other factors. when using external differential-mode clamping, it is important to ensure that the series resistors (r s ), the sum of the parasitic capacitance of the clamping devices, and the input capacitance of the ad8143 are small enough to preserve the desired signal bandwidth. figure 44 shows a specific example of external common-mode clamping. 05538-044 + ? v out v+ v+ v? v? 3 2 1 3 2 1 v in + ? r t r s r s hbat-540c hbat-540c figure 44. external common-mode clamping the series resistances, r s , limit the current in each leg, and the schottky diodes limit the voltages on each input to approximately 0.3 v to 0.4 v over the positive power supply, v+ and to 0.3 v to 0.4 v below the negative power supply, v?. the maximum value of r s is determined by the required signal bandwidth, the line impedance, and the effective differential capacitance due to the ad8143 inputs and the diodes. as with the differential clamp, the series resistors should be highly matched in value to preserve high frequency cmrr. printed circuit board layout considerations the two most important issues with regard to printed circuit board (pcb) layout are minimi zing parasitic signal trace reactances in the feedback network and providing sufficient thermal relief. excessive parasitic reactances in the feedback network cause excessive peaking in the amplifiers frequency response and excessive overshoot in its step response due to a reduction in phase margin. oscillation occurs when these parasitic reactances are increased to a critical point where the phase margin is reduced to zero. minimizing these reactances is important to obtain optimal performance from the ad8143. when operating at 12 v power, it is important to pay special attention to removing heat from the ad8143. besides the special layout considerations previously mentioned and expounded upon in the following sections, general high speed layout practices must be adhered to when applying the ad8143. controlled impedance transmission lines are required for incoming and outgoing signals, referenced to a ground plane.
ad8143 rev. 0 | page 21 of 24 typically, the input signals are received over 100 differential transmission lines. a 100 differential transmission line is readily realized on the printed circuit board using two well- matched, closely-spaced 50 single-ended traces that are coupled through the ground plane. the traces that carry the single-ended output signals are most often 75 for video signals. output signal connections should include series termination resistors that are matched to the impedance of the line they are driving. broadband power supply decoupling networks should be placed as close as possible to the supply pins. small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. minimizing parasitic reactances in the feedback network parasitic trace capacitance and inductance are both reduced when the traces that connect the feedback network together are reduced in length. removing the copper from all planes below the traces reduces trace capacitance, but increases trace inductance because the loop area formed by the trace and ground plane is increased. a reasonable compromise that works well is to void all copper directly under the feedback loop traces and component pads with margins on each side approximately equal to one trace width. combining this technique with minimizing trace lengths is effective in keeping parasitic trace reactances in the feedback loop to a minimum. additionally, all components used in the feedback network should be in 0402 surface-mount packages. figure 45 illustrates the magnified view of a proven feedback network layout that provides excellent performance. note that the internal layers are not shown. it is strongly recommended that the layout shown in figure 45 , or something very similar, be used for the three ad8143 feedback networks. a conservative estimate for feedback-loop trace capacitance in each loop of the layout shown in figure 45 is 2 pf. this value is viewed as the minimum load capacitance and is reflected in the frequency response and transient response plots. maximizing heat removal the ad8143 pinout includes ground connections on its corner pins to facilitate heat removal. these pins should be connected to the exposed paddle on the underside of the ad8143 and to a ground plane on the component side of the board. additionally, a 5 5 array of thermal vias connecting the exposed paddle to internal ground planes should be placed inside the pcb pad that is soldered to the exposed paddle. using these techniques is highly recommended in all applications, and is required in 12 v applications where power dissipation is the greatest. figure 45 illustrates how to optimize the circuit board layout for heat removal. designs must often conform to design-for-manufacturing (dfm) rules that stipulate how to lay out pcbs in such a way as to facilitate the manufacturing process. some of these rules require thermal relief on pads that connect to planes, and the rules may preclude the use of the technique illustrated in figure 45 . in these cases, the ground pins should be connected to the exposed paddle and component-side ground plane using techniques that conform to the dfm requirements. gnd gnd gnd gnd gnd gnd gnd c f r c f g r f g r g g r g b r g r r f b r f r c f b = circuit side = component side 05538-043 figure 45. recommended layout for feedback loops and grounding
ad8143 rev. 0 | page 22 of 24 driving a capacitive load the ad8143 typically drives either high impedance loads, such as crosspoint switch inputs, or doubly terminated coaxial cables. a gain of 1 is commonly used in the high impedance case because the 6 db transmission line termination loss is not incurred. a gain of 2 is required when driving cables to compensate for the 6 db termination loss. in all cases, the output must drive the parasitic capacitance of the feedback loop, conservatively estimated to be 2 pf, in addition to the capacitance presented by the actual load. when driving a high impedance input, it is recommended that a small series resistor be used to buffer the input capacitance of the device being driven. clearly, the resistor value must be small enough to preserve the required bandwidth. in the ideal doubly terminated cable case, the ad8143 output sees a purely resistive load. in reality, there is some residual capacitance, and this is buffered by the series termination resistor. figure 46 illustrates the high impedance case, and figure 47 illustrates the cable- driving case. 05538-053 r s c in r g r f + ? 0.01 f 0.01 f +5v ?5v fb ref v in figure 46. buffering the input capacitance of a high-z load 05538-054 r s c s r g r f + ? 0.01 f 0.01 f +5v ?5v fb ref v in r l figure 47. driving a doubly terminated cable small and large signal frequency responses for the high-z case with a 40 series resistor and 10 pf load capacitance are shown in figure 10 and figure 13 ; transient responses for the same conditions are shown in figure 18 and figure 21 . in the cable driving case shown in figure 47 , c s << 2 pf for a well-designed circuit; therefore, the feedback loop capacitance is the dominant capacitive load. the feedback loop capacitance is present for all cases, and its effect is included in the data presented in the typical performance characteristics and specifications tables. power-down the power-down feature is intended to be used to reduce power consumption when a particular device is not in use, and does not place the output in a high-z state when asserted. the power-down feature is asserted when the voltage applied to the power-down pin drops to approximately 2 v below the positive supply. the ad8143 is enabled by pulling the power-down pin to the positive supply. comparators in addition to general-purpose applications, the two on-chip comparators can be used to receive differential digital information or to decode video sync pulses from received common-mode voltages. built-in hysteresis helps to eliminate false triggers from noise. the comparator outputs are not designed to drive transmission lines. when the signals detected by the comparators are driven over cables or controlled impedance printed circuit board traces, the comparator outputs must be fed to a spare logic gate, fpga, or other device that is capable of driving signals over transmission lines. an internal linear voltage regulator derives power for the comparators from the positive supply; therefore, the ad8143 must always have a minimum positive supply voltage of 4.5 v. sync pulse extraction using comparators the ad8143 is particularly useful in keyboard video mouse (kvm) applications. kvm networks transmit and receive computer video signals, which are typically comprised of red, green, and blue (rgb) video signals and separate horizontal and vertical sync signals. because the sync signals are separate and not embedded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them among the three common-mode voltages of the rgb signals. the ad8134 triple differential driver is a natural complement to the ad8143 and performs the sync pulse encoding with the necessary circuitry on-chip.
ad8143 rev. 0 | page 23 of 24 where: the ad8134 encoding equations are given in equation 3, equation 4, and equation 5. [ ] (3) red v cm , green v cm , and blue v cm are the transmitted common- mode voltages of the respective color signals. hv k vred cm ?= 2 [ v2 2 ?= k vgreen cm ] (4) k is a an adjustable gain constant that is set by the ad8134 . [ hv k vblue cm += 2 ] (5) v and h are the vertical and horizontal sync pulses, defined with a weight of ?1 when the pulses are in their low states, and a weight of +1 when they are in their high states. the ad8134 data sheet contains further details regarding the encoding scheme. figure 48 illustrates how the ad8143 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the rgb common-mode voltages by the ad8134 . 05538-057 received red video hsync red cmv green cmv blue cmv 50 50 1k 1k vsync received green video 50 50 received blue video 50 50 figure 48. extracting sync signals from received common-mode signals
ad8143 rev. 0 | page 24 of 24 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.45 3.30 sq 3.15 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 49. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-3) dimensions shown in millimeters ordering guide model temperature range package description package option ad8143acpz-r2 1 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-3 AD8143ACPZ-REEL 1 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-3 AD8143ACPZ-REEL7 1 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-3 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05538C0C10/05(0)

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